1. Field of the Invention
This invention relates to integrated circuit manufacture and more particularly to a method of forming an interlevel dielectric structure having a high degree of surface planarity.
2. Description of the Relevant Art
An integrated circuit consists of electronic devices electrically coupled by conductive trace elements, often called interconnects. Interconnects are patterned from conductive layers formed on or above the surface of a silicon substrate. One or more layers can be patterned to form one or more levels of interconnects spaced from each other by one or more interlevel dielectric structures. Dielectric-spaced interconnect levels allow formation of densely patterned devices on relatively small substrate area.
An increase in the number of interconnect levels causes a corresponding increase in the elevational disparity of the resulting topological surface (i.e., an increase in the difference between the peaks and valleys of the resulting upper surface). Elevational disparity causes step coverage problems of interconnects placed over an interlevel dielectric peak and valley area. Elevational disparity also causes depth of focus problems of patterned interconnects formed on the interlevel dielectric. To reproduce fine line geometries, modern day optical steppers require small optical deviation of the interlevel dielectric surface to which the patterned interconnects are formed. In order to obtain maximum resolutions, imaging surfaces must be planar within .+-.0.5 microns. Sophisticated planarization techniques are therefore necessary to planarize the imaged surface. Planarization techniques are generally well known and exist in modern day fabrication processes.
Chemical vapor deposition (CVD) techniques typically yield conformal layers (i.e., layers which have the same thickness over horizontal and vertical surfaces). CVD is often used to deposit a dielectric layer over a substrate and/or over an interconnect level. When the thickness of the dielectric layer becomes appreciable relative to the distance between closely-spaced interconnects, undesirable air pockets (i.e., voids) may form between the closely-spaced interconnects. Either the CVD layer thickness must be minimized, or the interconnect spacing increased. Unfortunately, the former is more plausible than the latter due to the desire to increase the packing density and minimize the required surface area. If, however, the CVD layer thickness is decreased, other dielectric layers may be needed to complete an overall interlevel dielectric structure (i.e., a dielectric structure formed between interconnect levels).
Anisotropic CVD techniques present numerous advantages over conventional, isotropic CVD techniques employing standard LPCVD, PECVD and APCVD chambers. Anisotropic CVD has the ability to deposit material on horizontal surfaces at a faster rate than on vertical surfaces. Consequently, narrow spaces between closely-spaced interconnects can be filled with a dielectric material without creating substantial voids. Anisotropic CVD thereby produces a dielectric layer which is relatively thick on horizontal surfaces and relatively thin on vertical surfaces. Anisotropic CVD is particularly useful in forming a layer of dielectric upon a densely patterned underlayer of interconnects.
Another advanced CVD technique involves electron-cyclotron-resonance (ECR) CVD deposition. ECR is a relatively new plasma CVD technique in which deposition occurs simultaneously with sputter etching of the evolving layer. The high directionality of ECR plasma particles and simultaneous sputter etching produce a locally planar interlevel dielectric layer.
In addition to the CVD techniques, an interlevel dielectric layer can also be formed using a spin-on glass (SOG) material. Not only does SOG avoid creation of voids, but more importantly fills recesses or valleys as it flows across the upper surface prior to curing. Common SOG materials are siloxanes or silicates mixed in alcohol-based solvents. Applied to a wafer surface in liquid form, SOG materials typically flow over and fill narrow spaces between interconnects. Consequently, SOG materials produce a surface smoothing effect at isolated vertical edges. SOG materials are typically cured by baking to produce a hardened layer.
While anisotropic CVD, ECR plasma CVD, and SOG help planarize an upper surface during deposition, other techniques can be used to selectively remove surface material to planarize the surface after deposition. Namely, etch back steps can be employed either globally or locally to remove hills consistent with lower elevation valleys. More recent removal techniques utilize chemical-mechanical polishing (CMP). CMP applies both mechanical and chemical abrasion to an upper surface of a silicon wafer. During a CMP operation, a polishing pad saturated with an abrasive slurry solution is pressed against an upper surface of a silicon wafer. Movement of the pad relative to the wafer surface preferentially polishes elevated features on the upper surface. CMP thus increases surface planarity by reducing the heights of elevated features more so than the heights of structures in recessed areas. CMP can therefore be used to remove a dielectric surface at locally different rates which depend on the underlying pattern density. CMP is proven superior at quickly removing isolated or sparsely spaced upper elevational areas, while more slowly removing densely spaced upper elevational areas.
All of the above techniques have characteristics which limit their usefulness as a planarization method. Anisotropic CVD does not by itself increase the planarization of a surface since the upper elevational areas (hills) are increased similar to the lower elevational areas (valleys). ECR is able to increase the planarization of a surface, but throughput is limited as a result of simultaneous sputtering and further since few wafers can be processed simultaneously. SOG materials do not adhere well to metal interconnect lines, causing long-term reliability problems. SOG materials also tend to absorb water vapor which increases the resistance of electrical contacts formed in vias (i.e., holes etched through interlevel dielectric layers in order to electrically couple interconnect lines on different levels). A CMP process may have to be stopped before a high degree of planarity is reached in order to prevent the removal of too much surface material in certain critical areas. Further, CMP is useful to planarize isolated or sparsely spaced upper elevational areas. However, CMP leaves densely spaced upper elevational areas relatively intact. Despite their limitations, several of the above techniques may be advantageously combined into a highly effective interlevel dielectric planarization method, provided they are combined in a unique and advantageous fashion set forth hereinbelow.